Frequency divider circuits of various types are well known in the art. Such circuits generally include a signal processing path to perform the frequency division and a path from the output to the input to feedback the output state Japanese Patent No. 59-122128 (issued July 14, 1984) discloses a dynamic CMOS counter circuit that may be used as a frequency divider in which the state of the output of the circuit is fed back to control the state of an input storage terminal. The operating speed of a frequency divider is determined by the signal propagation delay through the circuit. The highest frequency at which the divider can operate is in large measure limited by the delay through the feedback path.
It is desirable to have an improved frequency divider which avoids feedback path delay and thereby provides faster operating speed and a higher operating frequency.